ISA
Originally one of IBM's proprietory buses, the ISA (Industry Standard Architecture) - also known as IBM Standard Architecture - started of as an 8-bit bus and was expanded to a 16-bit bus in 1984.
8 bit and 16 bit expansion slots used by PC, XT, and AT designs. The problems with the ISA bus grew as systems became faster and more powerful. The problems included: slow bus speed, a limited number of interrupts, lack of busmaster support, complex configuration and poor electrical grounding. Most of the problems were not significant early in the history of DOS computing, but came to the surface as the range of tasks and peripherals grew.
It also allows for bus mastering although only the first 16 MB of main memory is available for direct access. In reference to the XT bus architecture it is sometimes referred to as "AT bus architecture".
In 1993, Intel and Microsoft introduced a PnP ISA bus that allowed the computer to detect and setup computer ISA peripherals such as a NIC's and sound cards, negating the need to configure the device using jumpers or dipswitches. It was hit and miss at times, but definately a step forward.
The PCI bus effectively killed ISA off in the mid 90's. Even today (Dec 2002) you can buy new (low end) boards with a single ISA slot for these legacy devices but given that new operating systems like Microsoft XP won't recognise this bus, they are consigned to history.
EISA(Extended Industry Standard Architecture)
Announced in September of 1988, EISA was a standardised 32 bit operation computer bus designed by 9 competitors* to compete with IBM's MCA, or more specifically, the cost of it's licensing agreement. Still expensive, it was largely used for servers. Unfortunately, while the EISA bus is backwards compatible and is not a proprietary bus the EISA bus never became widely used and is no longer found in computers today.
*(These were: AST Research, Compaq, Epson, Hewlett Packard, NEC, Olivetti, Tandy, WYSE, and Zenith Data Systems).
The EISA Bus standard for IBM compatibles extended the ISA bus architecture to 32 bits and allowed for more than one CPU to share the bus. It provided 32-bit slots at an 8.33 MHz cycle rate for the use with 386DX, or higher processors. In addition the EISA could accommodate a 16-bit ISA card in the first row. It also enhanced to provide access to 4 GB of memory. Unlike MCA, EISA could accept older XT bus architecture and ISA boards.
MCA (Micro Channel Architecture)
MCA was introduced by IBM in 1987 as competition for the ISA BUS and was used by some (but not all) PS/2 models. The proprietary MCA bus offered several additional features over the ISA such as a 32-bit expansion bus designed for multiprocessing, automatically configured cards (similar to Plug and Play), and bus mastering for greater efficiency.
MCA was not compatible with either EISA or XT bus architecture so older cards cannot be used with it. Technically brilliant but ultimately killed by IBM's ridiculous licensing terms for the technology. Had IBM released this with little or do licencing fee the EISA bus would never have been designed nor, I believe, would PCI, instead MCA would have evolved continually.
VL-Bus Vesa Local Bus
Also abbreviated as VLB, it was introduced in 1992 and was up to 20 times faster than the ISA cards of the time in was intended to replace. The short lived, high speed, 32 bit extension bus gave direct access to the system memory at the speed of the processor, commonly the 486 CPU. Unfortunately, because the VLB heavily relied on the 486 processor, when the Pentium Processor was released manufacturers began switching to PCI.
Generically, a local bus is one connecting a processor to memory, usually on the same circuit board as opposed to a backplane and therefore faster.
VESA [ http://www.vesa.org/summary/sumvlbus.htm ] VL Bus - Intellectual property
PCI (Peripheral Component Interconnect)
High speed bus introduced by Intel in 1992 to support the demands of Pentium and 486 based computers. Technically far superior to VESA's local bus is rapidly replaced all this and all other buses of the time.
Revised in 1993 to version 2.0, and to PCI 2.1 in 1995, it is also available as a 64-bit bus.
PCI is supported by all major manufacturers including Apple Computer. It runs at 20 - 33 MHz and carries 32 bits at a time over a 124-pin connector or 64 bits over a 188-pin connector. An address is sent in one cycle followed by one word of data (or several in burst mode). Processor independent, it can work with other processor architectures as well.
Technically, PCI is not a bus but a bridge or mezzanine. It includes buffers to decouple the CPU from relatively slow peripherals and allow them to operate asynchronously.
The PCI bus is the standard bus on computers today (2002) for most computer expansion cards, although the video card moved to the AGP bus years earlier. PCI is due to be replaced by PCI Express over the next few years.
PCI-X
PCI-X is a 64-Bit high performance bus designed for servers to meet the high speed I/O demands of technologies like Fibre Channel, Gigabit Ethernet and Ultra3 SCSI. PCI-X capabilities include up to 133 MHz bus speed with 1GB/sec throughput.
Split Transactions allows an indicator device to make only one data request and relinquish the bus, instead of constantly needing to poll the bus for a response. A byte count that enables indicator to specify in advance the specific number of bytes requested, eliminating the inefficiency of speculative prefetches.
Backwards compatible, as far as I can tell a few revisions are planned and it will run in parallel with the upcoming PCI Express for some time. The trouble is, while this has the hearts of those in the server market, the complexities and extra costs to manufacture mean that they will be virtually unknown at the desktop level. PCI-X, for example, requires a controller for every slot and that is just too expensive. Enter the PCI Express...
PCI Express
This will be covered in depths under PCI Express
It is being formalised now (Fall of 2002) for release next year. Basically its a case of bigger, better, faster...
If I summed it up as initially 2.5Gb/s (20 fold PCI), up to 32x for the (16x for AGP replacement) AND backwards compatible...
AGP (Accelerated Graphics Port)
A bus specification introduced by Intel in 1997 which gives low-cost 3D graphics cards faster access to main memory on personal computers than the usual PCI bus.
AGP dynamically allocates the PC's normal RAM to store the screen image and to support texture mapping, z-buffering and alpha blending. AGP operates at 66 MHz, doubled to 133 MHz, compared with PCI's 33 Mhz. AGP allows for efficient use of frame buffer memory, thereby helping 2D graphics performance as well. It provides a coherent memory management design which allows scattered data in system memory to be read in rapid bursts. AGP reduces the overall cost of creating high-end graphics subsystems by using existing system memory.
Initially just AGP is has been advanced through 2x, 4x and 8x AGP with 16x AGP already proposed for release around 20004. I believe PCI Express will replace it before then though...
AMR (Audio/Modem Riser)
Released on September 8th 1998, AMR allowed OEM manufacturers like Asus to create one card that has the functionality of either Modem or Audio or both Audio and Modem on one card. This new specification allows for the motherboard to be manufactured at a lower cost and free up industry standard expansion slots in the system for other additional plug-in peripherals.
CNR (Communication and Network Riser)
An update to the CNR introduced by Intel on February 7th 2000. The CNR specification supports audio, modem USB and LAN interfaces of core logic chipsets.
| BUS |
Year |
Width |
Bus Speed (MHz) |
Bus Bandwidth (Mb/s) |
| 8-bit ISA | ~1981 | 8 | 8.3 | 7.9 |
| 16-bit ISA | 1984 | 16 | 8.3 | 15.9 |
| MCA | 1987 | 32 | 8.3 | . |
| EISA | 1988 | 32 | 8.3 | 31.8 |
| VLB | 1992 | 32 | 33 | 127.2 |
| PCI | 1992 (v2 1993) | 32 | 33 | 127.2 |
| PCI 2.1 66Mhz | 1994 | 64 | 66 | 508.6 |
| PCI 2.3, v3.0 | 2002/3 | 64 | 66 | . |
| PCI-X v1.0 | 1999 | 64 | 66 | . |
| PCI-X v1.0b, v2.0 | 2002/3 | 64 | 66 | . |
| PCI Express v1.0 | 2002/3 | 64 | 66 | 2,500* per lane in each direction. (initially) |
| AGP | ~1997 | 32 | 66 | 254.3 |
| AGP (x2) | ~1999 | 32 | 66x2 | 508.6 |
| AGP (x4) | ~2001 | 32 | 66x4 | 1,017.3 |
| AGP (x8) | 2002 | 32 | 66x8 | . |
* Each point-to-point interconnect may have 1, 2, 4, 8, 12, 16, or 32 dual simplex 2.5 Gbps lanes (2.0 Gbps effective rate), providing scalable bandwidth to 128 Gbps (16 gigabytes/second) between nodes
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